1. Field of the Invention
This invention relates to a multi-chip package (MCP) or multi-chip module (MCM) semiconductor device whereon a memory chip and logic chip are mounted, and to a semiconductor device wherewith it is possible to test the memory chip after accommodation in the package.
2. Description of the Related Art
Semiconductor devices called MCPs and MCMS are becoming widely used in which large-capacity memory chips and logic chips having specific functions such as functions for image processing and the like are mounted in the same package. FIG. 1 is a diagram of the configuration of a conventional MCP or MCM semiconductor device. In a common package 1 are mounted a high-speed, large-capacity memory chip 3 such as an SDRAM and a logic chip 2 having specific functions. In the logic chip 2 are provided a logic circuit 2A and an input/output circuit 2B for the memory chip 3, and around these circuits are further provided input/output terminals 20 to 25. And inside the memory chip 3 is deployed a cell array (not shown), while input/output terminals 32 to 37 are deployed about the periphery thereof.
In the package 1, external terminals 10 for connecting to the outside are provided. The external terminals 10 are connected to input/output terminals 20 of the logic chip 2 and to power supply terminals 36 and 37 of the memory chip 3 and the like via bonding wires or connection bumps. The memory chip 3 inputs and outputs data in response to access requests from the logic chip 2. Accordingly, the clock terminal 32, control signal terminal 33, address terminal 34, and data terminal 35 of the memory chip 3 are connected to corresponding terminals 22 to 25 of the logic chip.
Thus the memory chip 3 is only accessed from the logic chip 2, therefor the control signal terminal 33, address terminal 34, and data terminal 35 are connected to the logic chip 2 and are not connected directly to the external terminals of the package 1. Such a semiconductor device performs prescribed processing on prescribed data, stores the results thereof in the memory chip 3, and outputs those results to the outside.
Because the control signal terminal 33, address terminal 34, and data terminal 35 of the memory chip 3 are not connected to the outside of the package 1, as described above, the memory chip 3 cannot be adequately tested. Even if it is possible to conduct limited tests such as on the basic access operations to the memory chip 3 or the like, using the functions of the logic circuit 2A in the logic chip 2, tests cannot be performed on ordinary operations synchronized to high-frequency clock.
Even if limited tests could be performed on the memory chip 3 in the wafer condition, after it is mounted to the package 1, and after burn-in has been performed to enhance reliability, various tests cannot be performed as when a memory chip is mounted by itself.
It is possible to provide a built-in self testing circuit (BIST) inside the memory chip 3, but such a BIST circuit only performs operation tests inside the memory chip 3, and operation tests cannot be performed inclusive of determining whether the memory chip is operating normally to accesses from the logic chip 2 under the delay characteristics resulting from such connection means as wires or in-board interconnections that connect the logic chip 2 and the memory chip 3.
Thereupon, an object of the present invention is to provide a semiconductor device wherein a logic chip and memory chip are mounted in the same package and wherewith memory chip operation tests can be performed effectively.
Another object of the present invention is to provide a semiconductor device wherein a logic chip and memory chip are mounted in the same package, the memory chip is only accessed from the logic chip, and access operations from the logic chip to the memory chip can be performed effectively.
In order to attain the objects stated above, one aspect of the present invention is a semiconductor device wherein a logic chip having prescribed functions and a memory chip for storing data are mounted in a common package, wherein the logic chip and memory chip are connected through such memory access terminals which are a control signal terminal, address terminal, and data terminal and the like, and the logic chip has a logic circuit having the prescribed functions and a memory chip testing circuit for performing operation tests on the memory chip.
In a more preferable embodiment, the logic chip also has a selector-output circuit for selecting a memory access signal from the logic circuit and a memory testing access signal from the memory chip testing circuit to output the selected signal to the memory access terminal.
Based on the invention described in the foregoing, during ordinary operations, memory access signals from the logic circuit are sent to the memory chip via the selector-output circuit and access operations from the logic chip to the memory chip are performed, whereas, during memory chip testing, memory testing access signals from the memory chip testing circuit provided inside the logic chip are sent to the memory chip via the selector-output circuit, and access operations from the logic chip to the memory chip are tested. Accordingly, access operations, inclusive of delay times due to connection means between the logic chip and the memory chip, can be tested. In other words, even after package mounting and burn-in, high-speed access operation testing can be performed effectively.
In a preferable embodiment of the invention described in the foregoing, the logic chip also has a test control circuit for generating a first selection signal for selecting one or other of the memory access signal and the memory testing access signal in the selector-output circuit, in response to a test mode select signal from the outside.
In an even more preferable embodiment, the logic circuit has a plurality of macro circuits and random logic circuits having prescribed functions, and a macro selector for selecting such macro circuit or random logic circuit and connecting the selected circuit to an external terminal of the package, and the test control circuit generates a second selection signal for selecting from among the plurality of macro circuits and random logic circuits in the macro selector, in response to a test mode select signal from the outside.
In an even more preferable embodiment, the logic circuit has a plurality of logic circuit memories, and a memory selector for selecting those logic circuit memories and connecting the selected memory to an external terminal of the package, and the test control circuit generates a third selection signal for selecting from among the plurality of logic circuit memories in the memory selector, in response to a test mode select signal from the outside.
In a more preferable embodiment, moreover, the memory chip testing circuit has a memory chip control circuit for generating control signals for specifying memory chip operations, address signals, and write data according to a test mode, and a test data judgment circuit for comparing read data output by the memory chip in response to a read-out control signal from the memory chip control circuit and expected value data from the memory chip control circuit to output either match or mismatch to the outside of the package.
The memory chip testing circuit noted above also has an initialization circuit for initializing the memory chip, a self test circuit for testing the test data judgment circuit, and a test mode setting circuit for setting the test mode. The initialization circuit, self test circuit, and test mode setting circuit send respective mode signals to the memory chip control circuit in accordance with control data from outside the package. The memory chip control circuit generates the control signals, address signals, and write signals according to those mode signals.
In a more preferable embodiment of the invention described in the foregoing, the memory chip has a burn-in entry terminal for causing the interior thereof to enter into a burn-in operation. The memory chip also has a memory non-operate entry terminal for entering into a mode wherein the memory chip does not output an output signal during logic circuit testing. Both the burn-in entry terminal and the memory non-operate entry terminal are connected to an external terminal of the package. Thus, when the semiconductor device is being tested, the interior of the memory chip can easily be made to enter a burn-in operation mode or non-operation mode.
In a more preferable embodiment of the invention described in the foregoing, the logic chip has an inhibiting terminal for stopping internal operations of the logic chip, the inhibiting terminal is connected to an external terminal of the package. Thus, when the memory chip is being tested, it is prevented that the interior of the logic chip operating, power supply noise and the like is generated, so that the memory chip testing is subjected to adverse effects according to the noise.